Microprocessors Term paper
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The newest version of Transputer architectured chips is the INMOS T-9000, a processor containing 4 serial links, designed to be hooked up to other processors for parallel processing. The instruction set is minimized, as is the Sparc's RISC design, but is "based on a stack/accumulator design and designed around the OCCAM language". each chip containing 4 serial links to connect the chips in a network.The T-9000 was an attempt to regain the lead after more recent chips have surpassed previous transputers. The T-9000 basic architecture is that of the T-800 which contains "three 32 bit integer and three 64 bit floating point registers which are used as an evaluation stack - they are not general purpose." It uses memory addressed relative to the workspace, so access is slowed down with every 4 bits used for offset from the workspace register. The T-9000 has several levels of high speed caches and memory types, because of it's overwhelming speed. "The main cache is 16K, and is designed for 3 reads and 1 write simultaneously. The workspace cache is based on 32 word rotating buffers, allows 2 reads and 1 write simultaneously."The stack architecture makes instructions, in bytes, very compact, but executing one instruction byte per clock can be slow for multibyte instructions, so the T-9000 has a grouper which gathers instruction bytes (up to eight) into a single CISC-type instruction then sent into the 5 stage pipeline.This processor is ideal for parallel processing, " known as systolic arrays" (a pipeline is a simple example). Large networks can be created with the C104 crossbar switch, which can connect 32 transputers or other C104 switches into a network. "Transputers can adapt to a 64, 32, 16, or 8 bit bus. They can also feed off a 5 MHz clock, generating their own internal clock from this signal, and contain internal RAM, making them good for high performance embedded applications."However big delays in the T-9000 design "partly because of the stack based design"(T-9000) left it in the dust competitively with other CPUs .SPARC, Scalable Processor ARChitecture, was designed by Sun Microsystems for their own use. Existing manufacturers were slow to introduce a RISC processor, so Sun, a maker of workstations,went ahead and developed its own, based on Berkley's design and lesed it's design to other manufacturers.The original SPARC design was very unique, "even omitting multiple cycle multiply and divide instructions" which were added in later versions. SPARC usually contains about 128 or 144 registers. At each time 32 registers are available 8 are global, the rest are allocated in a 'window' from a stack of registers." The window...
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